In order to improve separation performance for a luminance signal (Y) and a chrominance signal (C), a motion adaptive three-dimensional Y/C separator has been incorporated in video processing equipment, such as TV receivers and VCRs. In these motion adaptive three-dimensional Y/C separators, a motion in a composite video signal is detected based on the magnitude of the inter-frame difference. This motion is then used for selecting between the processing of moving images and stationary images. Thus, a signal with a detected motion, i.e., a moving image, utilizes a Y/C separation implemented by an inter-line correlation, while a signal without such a detected motion, i.e., a stationary image, utilizes a Y/C separation implemented by an inter-frame correlation. Accordingly, in motion adaptive three-dimensional Y/C separators, precision of detecting motion has a significant influence on the performance of Y/C separation.
FIG. 1 shows a conventional video signal processor containing such a motion adaptive Y/C signal separation circuit. See, e.g., Miyazaki et al. "Development of Three-Dimensional Y/C Processing LSI", pp. 215-216, on Report in the 1989 National Meeting of the Television Society, the circuit of which will be incorporated herein as FIG. 1 for reference.
In FIG. 1, a composite video signal (e.g., NTSC signal) is applied to an A/D converter 102 through an input terminal 101. The A/D converter 102 converts the composite video signal to a digital form. The composite video signal is then applied to a moving image Y/C separation circuit 103 in a Y/C separation LSI 115. The moving image Y/C separation circuit 103 takes three consecutive line signals at a time, by using two 1H delay circuits ("H" represents one horizontal period) 104 and 105, to perform the Y/C separation for moving images. That is, the moving image Y/C separation circuit 103 first detects the vertical correlation of images from the horizontal low band components of the three consecutive line signals and then mixes two comblike filter outputs, based on the result of the vertical correlation, to obtain a vertical high frequency component (component not containing line correlation) for a center line signal and upper and lower line signals. The vertical high frequency component extracted by the moving image Y/C separation circuit 103 is then applied to a band-pass filter (hereinafter referred to as BPF) 106 wherein a color subcarrier band component is extracted from the vertical high frequency component. The color subcarrier band component is applied to both a subtracter 107 and a mixing circuit (hereinafter referred to as MIX circuit) 108 as a chrominance signal of moving images (hereinafter referred to the moving image C signal). The subtracter 107 receives another input from the 1H delay circuit 104 and subtracts the moving image C signal from the 1H delayed NTSC signal, thus resulting in a luminance signal of the moving image (hereinafter referred to as the moving image Y signal). This moving image Y signal is applied to another MIX circuit 109.
The NTSC signal on the output of the 1H delay circuit 104 is applied to a stationary image Y/C separation circuit 112 directly as well as through a one-frame delay circuit 110 with 525H (one-frame period) delay time. The stationary image Y/C separation circuit 112 separates a stationary image luminance signal (hereinafter referred to as the stationary image Y signal) by adding two frame signals with one-frame difference therebetween and a stationary chrominance signal component (frame non-correlative component) by subtracting the two frame signals. The stationary image Y signal separated in the stationary image Y/C separation circuit 112 is applied to the MIX circuit 109, while the chrominance signal component (frame non-correlative component) is applied to the MIX circuit 108 as the stationary chrominance signal (hereinafter referred to as the stationary image C signal) through another BPF 113.
The NTSC signal at the output of the 1H delay circuit 104 is applied to a motion detecting circuit 114. Furthermore the NTSC signal at the output of the one-frame delay circuit 110 is applied to the motion detecting circuit 114 directly as well as through another one-frame delay circuit 111 with 525H (one-frame period) delay time. Thus three consecutive frame signals obtained by the 1H delay circuit 104 and the two one-frame delay circuits 110 and 111 are applied to the motion detecting circuit 114. The motion detecting circuit 114 outputs the larger one of the motion signals detected based on an inter-frame difference between the outputs of the one-frame delay circuit 110 and the 1H delay circuit 104, and an inter-frame difference between the outputs of the 1H delay circuit 104 and the one-frame delay circuit 111. The motion signal from the motion detecting circuit 114 is applied to control terminals of the MIX circuits 108 and 109.
Thus the MIX circuit 109 receives the moving image Y signal and the stationary image Y signal, as well as the motion signal, as a control signal. The moving image Y signal and the stationary image Y signal are combined together at a ratio corresponding to the motion signal, so that a combined Y signal output from the MIX circuit 109 is obtained through a Y signal output terminal 116.
The MIX circuit 108 receives the moving image C signal and the stationary image C signal, as well as the motion signal, as a control signal. The moving image C signal and the stationary image C signal are combined together at the ratio corresponding tot he motion signal, so that a combined C signal output from the MIX circuit 108 is applied to a color processing LSI 117.
Additionally are shown synchronized processing LSI 140, abnormal detector 141, vertical and horizontal synchronized regenerator 142, feed forward ACC color filter and color phase adjustment 150, and burst detector 151.
In the conventional video signal processor, however, the motion detecting circuit 114 requires two large memories for configuring the one-frame delay circuits 110 and 111 as described above. Thus the conventional video signal processor has a disadvantage in cost and space for implementing the processor on IC chips.